1. Field of the Invention
This invention relates to electronic circuits and more specifically to a Transistor-Transistor Logic (TTL) output stage. The output stage of this invention is particularly useful with an ECL-TTL logic level translator circuit.
2. Description of the Prior Art
TTL output stages are known in the prior art. For example, the circuit of FIG. 1 provides an output signal on its output terminal 21 in response to an input signal received on its input terminal 12. With terminal 18 connected to a positive voltage VCC, and a logical one signal (i.e. a "high" signal of typically 5 volts) applied to input terminal 12, NPN transistors 13 and 15 are turned on, thus grounding output terminal 21. At the same time, the collector of transistor 13 is low, thus preventing NPN transistor 20 from turning on. Thus output terminal 21 provides a low output voltage in response to a high input signal applied to input terminal 12. Conversely, with a logical zero signal (i.e. a "low" signal of typically zero volts) applied to input terminal 12, transistor 13 is turned off, and the base of transistor 15 is grounded through resistor 14, thus causing transistor 15 to remain off. At the same time, with transistor 13 turned off, node 30 is held to a high voltage and diode 17 and transistor 20 turn on. With transistor 20 turned on, output terminal 21 is connected through resistor 19 to positive supply voltage VCC applied to terminal 18. Thus, output terminal 21 provides a high output voltage in response to a low input signal applied to input terminal 12.
One disadvantage of the prior art circuit of FIG. 1 is that the turnoff speed of transistor 15 in response to an input signal transition from a logical one to a logical zero, is rather slow. One approach to increase the turnoff speed of transistor 15 is shown in the circuit of FIG. 2a. With the addition of resistors 22 and 23 and NPN pulldown transistor 24, the turnoff speed of transistor 15 is increased. Such a so-called "squaring circuit" provided by resistors 22 and 23 and transistor 24 is described in U.S. Reissue Pat. No. 27,804 issued Oct. 30, 1973 on an invention of Treadway.
Yet another disadvantage in the prior art circuits of FIG. 1 and FIG. 2a is that, with a logical one applied to input terminal 12, a rather large amount of current flows through resistor 14 (FIG. 1) and resistors 14, 22 and 23 (FIG. 2a). Resistor 14 is typically very large. The main purpose of this resistor is to increase the breakdown voltage of transistor 15. Typically, this resistive pull down current may be as much as 1 milliamp per output circuit. On a typical integrated circuit device having many output circuits, the total resistive pull down current required is appreciable, thus adding significantly to the power requirements of the device.
Another TTL output stage is described in U.S. Pat. No. 4,311,927 issued Jan. 19, 1982 on an invention of Ferris and assigned to Fairchild Camera and Instrument Corporation, the assignee of this invention. The Ferris structure utilizes a unique circuit arrangement wherein the effects of the Miller capacitances are minimized.
An additional TTL output stage is shown in the circuit of FIG. 2b. The output stage of FIG. 2b utilizes diode D1 as a capacitor which momentarily causes pulldown transistor Q1 to conduct during the transistion of transistor Q4 from the conducting state to the non-conducting state. For example, with a logical one signal applied to input terminal A, transistor Q11 conducts, thus causing transistor Q4 to conduct, thereby grounding output terminal B. With transistor Q11 conducting, its collector (node 19) is low, thus causing transistors Q2 and Q3 to remain off. When a logical zero is applied to input terminal A, transistor Q11 turns off, the voltage on its collector (node 19) goes high, thus turning on transistors Q2 and Q3, thereby providing a high output signal at output terminal B. Simultaneously, with node 19 high, the capacitor provided by the reverse biased PN junction of diode D1 charges, thereby temporarily providing current flow between the base and emitter of pulldown transistor Q1, thereby temporarily turning on transistor Q1. With transistor Q1 conducting, the base of transistor Q4 is connected to ground, thereby forcing transistor Q4 to turn off quickly in response to a high to low transition of the input signal applied to input terminal A. However, as in the prior art circuit of FIG. 2a, the circuit of FIG. 2b utilizes pull down resistors R3 and R4 and transistor Q5 to conduct current from the emitter of transistor Q11 to ground, thereby adding to the current requirements of this output circuit.